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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
8-Input Data Selector/ Multiplexer With Data and Address Latches and 3-State Outputs
High-Performance Silicon-Gate CMOS
The MC54/74HC354 is identical in pinout to the LS354. The device inputs are compatible with Standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC354 selects one of eight latched binary Data Inputs, as determined by the Address Inputs. The information at the Data Inputs is stored in the transparent 8-bit Data Latch when the Data-Latch Enable pin is held high. The Address information may be stored in the transparent Address Latch, which is enabled by the active-high Address-Enable pin. The device outputs are placed in high-impedance states when Output Enable 1 is high, Output Enable 2 is high, or Output Enable 3 is low. The HC354 has a clocked Data Latch that is not transparent.
MC54/74HC354
J SUFFIX CERAMIC PACKAGE CASE 732-03
1
20
20 1
N SUFFIX PLASTIC PACKAGE CASE 738-03
20 1
DW SUFFIX SOIC PACKAGE CASE 751D-04
ORDERING INFORMATION MC54HCXXXJ MC74HCXXXN MC74HCXXXDW Ceramic Plastic SOIC
* * * * * * *
Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS and TTL Operating Voltage Range: 2 to 6V Low Input Current: 1A High Noise Immunity Characteristic of CMOS Devices In Compliance With the JEDEC Standard No. 7A Requirements Chip Complexity: 326 FETs or 81.5 Equivalent Gates LOGIC DIAGRAM
8 D0 7 D1 6 D2 5 D3 4 D4 3 D5 2 D6 1 D7
Pinout: 20-Lead Package (Top View)
D7 1 D6 2 D5 3 D4 4 D3 5 D2 6 20 VCC 19 Y 18 Y 17 OE3 16 OE2 15 OE1 14 A0 13 A1 12 A2 11 Address-Latch Enable
DATA INPUTS
8-BIT DATA LATCH (TRANS- PARENT)
8-BIT MULTI- PLEXER
3-STATE OUTPUT CONTROL
19 18
Y Y
3-STATE DATA OUTPUTS
D1 7 D0 8 Data-Latch 9 Enable GND 10
DATA-LATCH 9 ENABLE A0 ADDRESS INPUTS 14 13 A1 12 A2 ADDRESS LATCH (TRANS- PARENT) PIN 20 = VCC PIN 10 = GND
ADDRESS-LATCH 11 ENABLE OE1 OUTPUT ENABLES OE2 OE3 15 16 17
10/95
(c) Motorola, Inc. 1995
1
REV 7
IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I III I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I III I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I IIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII III IIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII
MC54/74HC354
MAXIMUM RATINGS*
Symbol VCC Vin Parameter Value Unit V V V DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) - 0.5 to + 7.0 - 1.5 to VCC + 1.5 - 0.5 to VCC + 0.5 20 35 75 750 500 Vout Iin DC Output Voltage (Referenced to GND) DC Input Current, per Pin mA mA mA Iout DC Output Current, per Pin ICC PD DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic or Ceramic DIP SOIC Package Storage Temperature Range mW Tstg TL - 65 to + 150 260 300
_C _C
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
v
v
Lead Temperature, 1 mm from Case for 10 Seconds Plastic DIP or SOIC Package Ceramic DIP
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C Ceramic DIP: - 10 mW/_C from 100_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I III I I I I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII I I III I I III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I
RECOMMENDED OPERATING CONDITIONS
Symbol VCC Parameter Min 2.0 0 Max 6.0 Unit V V DC Supply Voltage (Referenced to GND) Vin, Vout TA DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature Range, All Package Types Input Rise/Fall Time (Figure 1) VCC - 55 0 0 0 + 125 1000 500 400
_C
ns
tr, tf
VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V
DC CHARACTERISTICS (Voltages Referenced to GND)
Symbol VIH Parameter Minimum High-Level Input Voltage
Condition Vout = 0.1V or VCC -0.1V |Iout| 20A Vout = 0.1V or VCC - 0.1V |Iout| 20A Vin = VIH or VIL |Iout| 20A Vin =VIH or VIL |Iout| 6.0mA |Iout| 7.8mA
VCC V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0
Guaranteed Limit -55 to 25C 1.50 3.15 4.20 0.3 0.9 1.2 1.9 4.4 5.9 3.98 5.48 0.1 0.1 0.1 0.26 0.26 0.1 85C 1.50 3.15 4.20 0.3 0.9 1.2 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 1.0 125C 1.50 3.15 4.20 0.3 0.9 1.2 1.9 4.4 5.9 3.70 5.20 0.1 0.1 0.1 0.40 0.40 1.0 A V Unit V
VIL
Maximum Low-Level Input Voltage
V
VOH
Minimum High-Level Output Voltage
V
VOL
Maximum Low-Level Output Voltage
Vin = VIH or VIL |Iout| 20A Vin = VIH or VIL |Iout| 6.0mA |Iout| 7.8mA
4.5 6.0 6.0
Iin
Maximum Input Leakage Current
Vin = VCC or GND
MOTOROLA
2
High-Speed CMOS Logic Data DL129 -- Rev 6
MC54/74HC354
DC CHARACTERISTICS (Voltages Referenced to GND)
Symbol IOZ Parameter Maximum Three-State Leakage Current Maximum Quiescent Supply Current (per Package) Condition Output in High-Impedance State Vin = VIL or VIH Vout = VCC or GND Vin = VCC or GND Iout = 0A VCC V 6.0 Guaranteed Limit -55 to 25C 0.5 85C 5.0 125C 10.0 Unit A
ICC
6.0
8
80
160
A
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Symbol tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLZ, tPHZ tPZL, tPZH tTLH, tTHL Cin Cout Parameter Maximum Propagation Delay, D0-D7 to Y or Y (Figures 2 and 6) Maximum Propagation Delay, Data-Latch Enable to Y or Y (Figures 3 and 6) Maximum Propagation Delay, A0-A2 to Y or Y (Figures 2 and 6) Maximum Propagation Delay, Address-Latch Enable to Y or Y (Figures 3 and 6) Maximum Propagation Delay, OE1-OE3 to Y or Y (Figures 4 and 7) Maximum Propagation Delay, OE1-OE3 to Y or Y (Figures 4 and 7) Maximum Output Transition Time, Any Output (Figures 1 and 6) Maximum Input Capacitance Maximum Three-State Output Capacitance (Output in High Impedance State) VCC V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Guaranteed Limit -55 to 25C 210 42 36 260 52 44 270 54 46 270 54 46 160 32 27 125 25 21 60 12 10 10 15 85C 265 53 45 325 65 55 340 68 58 340 68 58 200 40 34 155 31 26 75 15 13 10 15 125C 315 63 54 390 78 66 405 81 69 405 81 69 240 48 41 190 38 32 90 18 15 10 15 Unit ns
ns
ns
ns
ns
ns
ns
pF pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High- Speed CMOS Data Book (DL129/D). Typical @ 25C, VCC = 5.0 V CPD Power Dissipation Capacitance (Per Package)* 48 pF * Used to determine the no-load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
High-Speed CMOS Logic Data DL129 -- Rev 6
3
MOTOROLA
MC54/74HC354
PIN DESCRIPTIONS
D0-D7 (Pins 8-1) DATA INPUTS These eight data bits are stored in a transparent latch when the Data-Latch Enable pin is active (high). Once enabled, changing inputs will not change the contents of the latch. A0, A1, A2 (Pins 14,13,12) ADDRESS INPUTS Selects which data bit stored in the Data Latch is routed to the outputs Y and Y. DATA-LATCH ENABLE (Pin 9) The latch is transparent to D0-D7 when enable is inactive (low). The Data-Latch contents are unaffected when enable is held active (high). ADDRESS-LATCH ENABLE (Pin 11) The latch is transparent to A0, A1 and A2 when enable is inactive (low). The Address-Latch contents are unaffected when enable is held active (high). OE1, OE2, OE3 (Pins 15,16,17) OUTPUT ENABLES Any of the output enable pins inactive (OE1=High or OE2=High or OE3=Low) causes the outputs (Y and Y) to be in high-impedance states. Y, Y (Pins 19,18) These 3-state outputs (when not 3-stated) represent the data bit in the Data Latch selected by the Address Latch.
TIMING REQUIREMENTS (Input tr = tf = 6 ns)
Symbol tsu Parameter Minimum Setup Time, D0-D7 to Data-Latch Enable (Figure 5) Minimum Setup Time, A0-A2 to Address-Latch Enable (Figure 5) Minimum Hold Time, Data-Latch Enable to D0-D7 (Figure 5) Minimum Hold Time, Address-Latch Enable to A0-A2 (Figure 5) Minimum Pulse Width, Data-Latch Enable (Figure 3) Minimum Pulse Width, Address-Latch Enable (Figure 3) Maximum Input Rise and Fall Times (Figure 1) VCC V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Guaranteed Limit -55 to 25C 50 10 9 50 10 9 5 5 5 5 5 5 80 16 14 80 16 14 1000 500 400 85C 65 13 11 65 13 11 5 5 5 5 5 5 100 20 17 100 20 17 1000 500 400 125C 75 15 13 75 15 13 5 5 5 5 5 5 120 24 20 120 24 20 1000 500 400 Unit ns
tsu
ns
th
ns
th
ns
tw
ns
tw
ns
tr, tf
ns
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
MOTOROLA
4
High-Speed CMOS Logic Data DL129 -- Rev 6
MC54/74HC354
FUNCTION TABLE
Address Latch Contents # A2 X X X L L L L H H H H L L L L H H H H A1 X X X L L H H L L H H L L H H L L H H A0 X X X L H L H L H L H L H L H L H L H Data-Latch Enable X X X L Inputs OE1 H X X L OE2 X H X L OE3 X X L H Outputs Y Z Z Z D0 D1 D2 D3 D4 D5 D6 D7 Y Z Z Z D0 D1 D2 D3 D4 D5 D6 D7 Description Outputs in High-Impedance States
Data-Latch is Transparent
D0n D0n New Data is Stored in Data-Latch and is D1n Not Alterable D1n D2n D2n D3n D3n D4n D4n D5n D5n D6n D6n D7n D7n # Represents bits in Address-Latch. See Address-Latch Enable pin description. X = Don't Care; Z = High Impedance; D0-D7 = the data at inputs D0 through D7; D0n-D7n = the data present at inputs D0 through D7 when the Data-Latch Enable pin was taken high.
H
L
L
H
SWITCHING WAVEFORMS
tr Any Input 90% 10% tf VCC GND D0-D7 A0-A2 tPLH Y or Y 90% 10% tTLH tTHL Y or Y 50% 50% GND tPHL VALID VALID VCC
Figure 1.
Figure 2.
OE1, OE2 50% tw Address- Latch Enable VCC 50% GND tPLH Y or Y 50% Y or Y 50% tPHL Y or Y 50% tPZH tPHZ 90% 10% OE3 tPZL tPLZ
VCC GND High Impedance VOL VOH High Impedance
Figure 3.
Figure 4.
High-Speed CMOS Logic Data DL129 -- Rev 6
5
MOTOROLA
MC54/74HC354
Valid D0-D7 A0-A2 VCC 50% GND tsu Data-Latch Enable 50% GND th VCC
Figure 5.
TEST CIRCUITS
TEST POINT OUTPUT DEVICE UNDER TEST CL* DEVICE UNDER TEST OUTPUT TEST POINT 1k CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ and tPZH.
CL*
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 6.
Figure 7.
MOTOROLA
6
High-Speed CMOS Logic Data DL129 -- Rev 6
MC54/74HC354
15
Output Enables
OE1 16 OE2 OE3 A0
17
14
D
Q
LE Q Address Inputs A1
13
D
Q
LE Q A2
12
D
Q
LE Q Address- 11 Latch Enable D0
8
D LE Q
D1
7
D LE Q
D2
6
D LE Q
19
D3 Data Inputs D4
5
Y
D LE Q 3-State Data Outputs
18
4
D LE Q Y
D5
3
D LE Q
D6
2
D LE Q
D7
1
D LE Q
Data-Latch 9 Enable
Figure 8. Expanded Logic Diagram
High-Speed CMOS Logic Data DL129 -- Rev 6
7
MOTOROLA
MC54/74HC354
OUTLINE DIMENSIONS
J SUFFIX CERAMIC PACKAGE CASE 732-03 ISSUE E
B A F C L
DIM A B C D F G H J K L M N NOTES: 1. LEADS WITHIN 0.25 (0.010) DIAMETER, TRUE POSITION AT SEATING PLANE, AT MAXIMUM MATERIAL CONDITION. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSIONS A AND B INCLUDE MENISCUS. MILLIMETERS MIN MAX 23.88 25.15 6.60 7.49 3.81 5.08 0.38 0.56 1.40 1.65 2.54 BSC 0.51 1.27 0.20 0.30 3.18 4.06 7.62 BSC 0_ 15 _ 0.25 1.02 INCHES MIN MAX 0.940 0.990 0.260 0.295 0.150 0.200 0.015 0.022 0.055 0.065 0.100 BSC 0.020 0.050 0.008 0.012 0.125 0.160 0.300 BSC 0_ 15_ 0.010 0.040
20 1
11 10
N H D
SEATING PLANE
G
K
J M
-A-
20 11
N SUFFIX PLASTIC PACKAGE CASE 738-03 ISSUE E
B
1
10
C
L
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01
-T-
SEATING PLANE
K M E G F D
20 PL
N J 0.25 (0.010)
M 20 PL
0.25 (0.010) TA
M
M
TB
M
DIM A B C D E F G J K L M N
-A-
20 11
DW SUFFIX PLASTIC SOIC PACKAGE CASE 751D-04 ISSUE E
10X
-B-
1 10
P 0.010 (0.25)
M
B
M
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.150 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 12.65 12.95 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0_ 7_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.499 0.510 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0_ 7_ 0.395 0.415 0.010 0.029
20X
D
M
0.010 (0.25)
TA
S
B
J
S
F R X 45 _ C -T-
18X SEATING PLANE
G
K
M
MOTOROLA
8
High-Speed CMOS Logic Data DL129 -- Rev 6
MC54/74HC354
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High-Speed CMOS Logic Data DL129 -- Rev 6
CODELINE
9
*MC54/74HC354/D*
MC54/74HC354/D MOTOROLA

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